1. Field of the Invention
The present invention relates generally to interface circuits, and specifically, to a circuit for allowing full forward current and throttling reverse current in an output stage MOS transistor.
2. Background Information
A metal oxide semiconductor ("MOS") transistor is a bilateral device. When the MOS transistor is on, current may flow in either direction depending on the ON resistance and the differential voltage across the device. In specific applications, such as a CMOS driver connected to a multi-party line, it is desirable for current to flow freely in one direction, and to be greatly restricted in the opposing direction. In a transmitter driver application for a three volt interface circuit, there are the combined requirements for high forward drive currents (e.g., greater than 10 mA) at a low Vds (e.g., 0.2 Volts) and a very low (or zero) reverse current. Forward current is defined as a positive current flowing from the positive supply (VCC) through the MOS device to the output or from the output through the MOS device into the negative supply (VEE or GND). Except for the forward voltage drop across a diode (Vbe), the diode (p-n junction) exhibits the required circuit function.
An active rectification circuit can provide the required function but there are accuracy and hysteresis problems in determining when the MOS transistor should and should not conduct. For example, in the transmitter driver application where the driver is attached to a multi-party line, the MOS transistor must be able to protect against the potential for reverse current which may be caused by an external circuit pulling the output beyond the supply rails, by noise, or by ringing due to improper line termination. If the MOS transistor turns off at an output voltage beyond the supply rail, significant reverse current may flow, depending on the MOS transistor ON resistance, until the turn off voltage is reached.
In the case of a power supply with a high output resistance (as with a battery) the reverse current may result in back-charging the supply, which can be destructive to a non-rechargeable battery. The MOS device must also behave properly when nothing external is driving the output, and there is only an external load with resistance ranging from a short circuit up to and including an open circuit. If the MOS transistor turns completely off prior to the output reaching the supply rail voltage, an external load can cause the output to droop. It will continue to droop due to the external load until the MOS device again turns on. The difference in the output voltage from turn off to turn on is the hysteresis of the active rectification circuit. When the MOS transistor is turned off prior to the output reaching the supply voltage, the output will "chatter", oscillating between turn off and turn on voltages.
FIG. 1 illustrates a prior art output interface circuit. Referring to FIG. 1, four series connected MOS transistors MP1, MP2, MN2 and MN1 are shown. This represents a low voltage MOS transmitter driver as shown in U.S. Pat. No. 5,414,314 issued to Thurber and assigned to the assignee of the present invention. Under normal transmitter enabled conditions, MP1 and MN1 remain fully-on, and MP2 and MN2 are switched in such a way that MP2 or MN2 is on to drive VOUT high or low, respectively, but both are never on together.
The addition of MP1 and MN1 to the elementary switching circuit provides a means for active rectification. The incentive for the addition of MP1 and MN1 in lieu of diodes is to eliminate the forward Vbe of the diodes. The forward Vbe is typically greater than 0.8 Volts at temperature. This voltage is replaced by the Vds (drain-to-source voltage) of a MOS device, which is a size/strength dependent variable, but typically sized to never exceed 0.3 Volts.
FIG. 2 illustrates a cross section of the prior art output interface circuit. For purposes of illustration, FIG. 2 shows a P-well process with isolated pockets on a p-type substrate. However, the output interface circuit may equally be built in an n-well process. Referring to FIGS. 1 and 2, PMOS devices MP1 and MP2 are isolated in a local n- pocket 10. The potential of the n- pocket 10 is that of Node P1 and is maintained by the voltage on the common sources 14 and 16 of MP1 and MP2, when either or both of MP1 and MP2 are on, in parallel with the p+(12)/n-(10) diode DP1 and the P+(18)/n-(10) diode DP2. These diodes are called "body diodes" and are present by virtue of the semiconductor materials which create the MOS devices. Moreover, NMOS devices MN1 and MN2 are isolated in a second local n- pocket 20. The potential of this pocket is held at VCC. Within the second n- pocket (20) is a P-well (p-) 30 where the NMOS devices are contained. The potential of the P-well 30 is that of the Node W1 and is maintained by the voltage on the common sources 26 and 24 of MN1 and MN2, when either or both of these devices are on, in parallel with the p-(30)/n+(28) body diode DN1 and the p-(30)/n+(22) body diode DN2.
Referring back to FIG. 1, voltage sensitive detection circuitry is constantly monitoring VOUT relative to VCC and GND. In the case of active rectification, when VOUT is determined to be at or above VCC, gate GP1 is connected to Node P1 which turns off MP1. A small current flows from VOUT through MP2, if ON, or through DP2 if MP2 is OFF, which will charge up Node P1 to the VOUT voltage level. Once charged up to VOUT, no more current will flow.
A complementary action takes place on the NMOS side of the circuit when VOUT is determined to be at or below GND. In this instance, gate GN1 is connected to Node W1. This turns off MN1. A small current flows from W1 through MN2, if ON, or through DN2 if MN2 is OFF, to discharge W1 to the VOUT voltage level.
The embodiment shown in FIGS. 1 and 2 suffers from the real world inaccuracies as described above. Namely, the actual measurement of VOUT includes typical offset errors. To avoid the "chatter" problem described above, the measurement must be biased to delay the turn off point until VOUT exceeds VCC (or GND) by at least the worst case offset. Once VOUT exceeds VCC (or GND), reverse current can flow. At the point at which the state of the output is switched, significant reverse current may flow, and in the case of a high impedance supply, the VCC (or GND) may be pulled with VOUT and "turn off" may never occur.